The present invention relates to a semiconductor device, and more particularly to the structure of an MOS or MIS semiconductor device and a method of producing the same.
In recent years, the trend toward increasing levels of circuit integration is underway in semiconductor devices. This also applies to MOS transistors, and the circuit dimensions of this type of device have become extremely small, reaching even submicron regions. As such a trend toward smaller circuit dimensions progresses, a phenomenon called punch-through takes place in which a current flows between a source and a drain irrespective of the gate voltage. To solve this problem, a method for increasing the density of impurities in a portion deeper than a substrate surface are known, as disclosed in Japanese Patent Publication No. 16194/1979 and Japanese Patent Laid-Open Applications Nos. 127273/1978, 180167/1985, and 235471/1985. A description will be given of this method with reference to FIG. 2. In FIG. 2, reference numeral 201 denotes a p-type semiconductor substrate, such as a P-type silicon substrate; 202, an element isolating insulation film; 203, a gate insulating film; 209, a source region and a drain region both formed of an n-type layer of high-concentration impurities; 205, a gate electrode; and 204, a p-type layer of impurities having a higher concentration of impurities than the semiconductor substrate 201. Even if the depletion layer of the drain spreads on application of a voltage to the drain, the spreading of the depletion layer is held by the p-type layer of impurities 204, thereby preventing the occurrence of a punch-through.
In addition, if the trend toward smaller circuit dimensions is advanced with a supply voltage fixed, deterioration of characteristics occurs due to hot carriers. To solve this problem, a structure called an LDD (lightly doped drain) was proposed. However, a structure in which further improvements are made on this LDD is disclosed in the following literature 1: Ching-Yeu Wei, J. M. Pimbley, Y. Nissan-Cohen, "Buried and Graded/Buried LDD structures for Improved Hot-Electron Reliability", IEEE Electron Device Lett., Vol. EDL-7, No. 6, pp. 380-382, Jun. 1986. A description of this structure will be given with reference to FIG. 3. In FIG. 3, reference numeral 301 denotes a p-type silicon substrate formed of a p-type semiconductor; 302, an element isolating insulating film formed of an oxide film or the like; 303, a gate insulating film formed of an oxide film or the like; 305, a gate electrode; 309, a source region and a drain region both formed of an n-type layer of high-concentration impurities; 306, a source region and a drain region both formed of an n-type layer of low-concentration impurities; 308, a side wall insulating film; and 304, a p-type layer of impurities having a higher concentration of impurities than the semiconductor substrate 30. The source region and the drain region formed of the n-type layer 306 of low-concentration impurities is deeper than the channel of an MOS-type transistor, and extends inwardly of the gate electrode. As a result, since the passage of a circuit flowing through the channel is bent downward at a drain end, and a spot where hot carriers are generated also moves to the inside of the substrate, it has been known that the frequency at which the generated hot carriers jump into the interface between the gate oxide film and the channel is reduced, thereby minimizing the deterioration rate of the MOS transistor due to hot carriers.
However, since in the conventional example shown in FIG. 2 the concentration of impurities in a portion deeper than the substrate surface is made higher, a punch-through is unlikely to occur, but since no measures have been taken with respect to the concentration of an electric field in the vicinity of a drain, there has been a problem in that the characteristics become deteriorated due to hot carriers.
In addition, although in the conventional example shown in FIG. 3 deterioration of the characteristics due to hot carriers is minimized, there has been a drawback in that since the source region and the drain region project inwardly of the gate electrode, a drain depletion layer and a source depletion layer are liable to be connected to each other, possibly resulting in a punch-through. Furthermore, since the threshold voltage of the MOS transistor is also involved, if the p-type layer 304 having a concentration of impurities higher than that of the semiconductor substrate 301 is formed in the vicinity of the surface of the semiconductor substrate 301, an avalanche phenomenon is liable to occur in the vicinity of the surface, with the adverse result that the deterioration of the MOS transistor becomes great.